The present invention relates generally to semiconductor technology, and more particularly, to a stack package.
In order to accommodate the demands for miniaturization and high performance, new techniques for providing a semiconductor module of high capacity are required. One method for providing a semiconductor module of high capacity is to manufacture a highly integrated memory chip. High integration of a memory chip is accomplished by integrating an increased number of cells in the already limited space of the semiconductor chip.
However, high integration of a memory chip requires both high precision techniques, such as a technique for attaining a fine line width, and a lengthy development period. With these limitations in mind, stacking techniques have been suggested as another method for providing a semiconductor module of high capacity.
Two such stacking techniques include a first method of embedding two stacked chips in a single package and a second method of stacking two separate packages which are independently packaged. Recently, another technique has been discovered, in which through-electrodes made of a conductive material such as copper are formed in semiconductor chips in such a manner that the semiconductor chips can be electrically connected by the through-electrodes when they are stacked.
By using through-electrodes, I/O pads can be bonded with a fine pitch allowing the number of I/O pads to be increased. Further, signal transmission speed among the semiconductor chips can be improved due to the formation of an increased number of I/O pads. Also, since three-dimensional design of semiconductor chips is enabled, the performance of the semiconductor chips can be enhanced.
When manufacturing a stack package such that electrical connections between upper and lower semiconductor chips are formed through through-electrodes, if the size of a downwardly positioned chip (hereinafter referred to as a “lower chip”) and an upwardly positioned chip (hereinafter referred to as an “upper chip”) are different, defects are likely to occur. For example, in the event that the lower chip has a size smaller than the upper chip, the stack may be implemented while the upper chip is in a structurally unstable state, and the stack itself may be impossible.